1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a standard cell used for a cell-base design.
2. Background Art
In recent years, Shallow Trench Isolation (STI) for device isolation has been used in CMOS processes. It is known that because of finer design rules in the CMOS processes, the threshold values of CMOS transistors are affected by stresses caused by STI.
For example, the shorter the distance from STI to the channel of a MOS transistor, the greater the stress of STI on the channel. Thus the current driving capability of an n-type MOS transistor decreases and the current driving capability of a p-type MOS transistor increases. In other words, it is difficult to predict the performance of a formed MOS transistor.
In order to avoid the influence of a stress caused by STI, it is necessary to increase a distance from STI to the channel of the MOS transistor.
However, a long distance from STI to the channel of the MOS transistor results in a large cell layout.
In the case where a semiconductor integrated circuit is designed by combining a plurality of function blocks called standard cells having uniform heights and power supply wiring configurations, it is difficult to increase the distance from STI to the channel to avoid the influence of a stress caused by STI.
In some conventional semiconductor integrated circuits, dummy MOS transistors are used for device isolation (for example, see U.S. Pat. No. 4,570,176).
However, the conventional art is not premised on standard cells or is not devised in consideration of the influence of a stress caused by STI or leak current of the dummy MOS transistors.